MSC8103SLASHD datasheet(16/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

1-12

Freescale Semiconductor

Signals/Connections

IRQ5

DP5

DREQ4

EXT_DBG3

Input

Input/Output

Input

Output

Interrupt Request 51

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 51

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity five pin should give odd parity (odd number of ones) on the group of signals that includes data

parity 5 and D[40–47].

DMA Request 41

An external peripheral uses this pin to request DMA service.

External Data Bus Grant 31,2

The MSC8103 asserts this pin to grant data bus ownership to an external bus master.

IRQ6

DP6

DACK3

Input

Input/Output

Output

Interrupt Request 61

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 61

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity six pin should give odd parity (odd number of ones) on the group of signals that includes data

parity 6 and D[48–55].

DMA Acknowledge 31

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

IRQ7

DP7

DACK4

Input

Input/Output

Output

Interrupt Request 71

One of eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Data Parity 71

The master or slave that drives the data bus also drives the data parity signals. The value driven on

the data parity seven pin should give odd parity (odd number of ones) on the group of signals that

includes data parity 7 and D[56–63].

DMA Acknowledge1

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

Input/Output

Transfer Acknowledge

Indicates that a data beat is valid on the data bus. For single beat transfers, assertion of TA

indicates the termination of the transfer. For burst transfers, TA is asserted four times to indicate the

transfer of four data beats with the last assertion indicating the termination of the burst transfer.

TEA

Input/Output

Transfer Error Acknowledge

Indicates a bus error. masters within the MSC8103 monitor the state of this pin. The MSC8103

internal bus monitor can assert this pin if it identifies a bus transfer that is hung.

NMI

Input

Non-Maskable Interrupt

When an external device asserts this line, the MSC8103 NMI input is asserted.

NMI_OUT

Output

Non-Maskable Interrupt

Driven from the MSC8103 internal interrupt controller. Assertion of this output indicates that a

non-maskable interrupt, pending in the MSC8103 internal interrupt controller, is waiting to be

handled by an external host.

PSDVAL

Input/Output

Data Valid

Indicates that a data beat is valid on the data bus. The difference between the TA pin and PSDVAL

is that the TA pin is asserted to indicate data transfer terminations while the PSDVAL signal is

asserted with each data beat movement. Thus, when TA is asserted, PSDVAL is asserted, but when

PSDVAL is asserted, TA is not necessarily asserted. For example when the SDMA initiates a double

word (2x64 bits) transfer to a memory device that has a 32-bit port size, PSDVAL is asserted three

times without TA, and finally both pins are asserted to terminate the transfer.

Table 1-5.

System Bus, HDI16, and Interrupt Signals (Continued)

Signal

Data Flow

Description

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