MSC8103SLASHD datasheet(32/104 Pages) FREESCALE

32 / 104 page

MSC8103 Network Digital Signal Processor, Rev. 11

1-28

Freescale Semiconductor

Signals/Connections

PC24

BRG8O

CLK8

TIN3

Timer4: TOUT4

DMA: DREQ2

Output

Input

Output

Input

Baud-Rate Generator 8 Output

The CPM supports up to 8 BRGs used internally by the bank-of-clocks

selection logic and/or to provide an output to one of the 8 BRG pins.

Clock 8

The CPM supports up to 10 clock input pins. The clocks are sent to the

bank-of-clocks selection logic, where they can be routed to the controllers.

Timer Input 3

A timer can have one of the following sources: another timer, system

clock, system clock divided by 16, or a timer input. The CPM supports up

to four timer inputs. The timer inputs can be captured on the rising, falling,

or both edges.

Timer 4: Timer Out 4

The timers (Timer1–4]) can output a signal on a timer output (TOUT[1–4])

when the reference value is reached. This signal can be an active-low

pulse or a toggle of the current output. The output can also be connected

internally to the input of another timer, resulting in a 32-bit timer.

DMA: Data Request 2

DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA controller.

DONE2 and DRACK2 are signals on the same pin and therefore cannot be

used simultaneously. There are two sets of DMA pins associated with the

PIO ports.

PC23

CLK9

DMA: DACK1

EXT2

Input

Output

Input

Clock 9

The CPM supports up to 10 clock input pins sent to the bank-of-clocks

selection logic, where they can be routed to the controllers.

DMA: Data Acknowledge 1

DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller.

DONE1 and DRACK1 are signals on the same pin and therefore cannot be

used simultaneously. There are two sets of DMA pins associated with the

PIO ports.

External Request 2

External request input line 2 asserts an internal request to the CPM

processor. The signal can be programmed as level- or edge-sensitive, and

also has programmable priority. Refer to the risc controller configuration

MSC8103 Reference

Manual for programming information. There are no current microcode

applications for this request line. It is reserved for future development.

Table 1-9.

Port C Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

MSC8103/D 数据表(PDF) 32 Page - Freescale Semiconductor, Inc

MSC8103/D 数据表(HTML) 32 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

MSC8103/D 数据表(PDF) 32 Page - Freescale Semiconductor, Inc

MSC8103/D 数据表(HTML) 32 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载