MSC8103SLASHD datasheet(41/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

2-1

Physical and Electrical Specifications

This document contains detailed information on environmental limits, power considerations, DC/AC electrical

characteristics, and AC timing specifications for the MSC8103 communications processor, mask set 2K87M. For

additional information, see the MSC8103 Reference Manual.

2.1 Absolute Maximum Ratings

In calculating timing requirements, adding a maximum value of one specification to a minimum value of another

specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation

of process parameter values in one direction. The minimum specification is calculated using the worst case for the

same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the

same device with a “minimum” value for another specification; adding a maximum to a minimum represents a

condition that can never exist. Table 2-1 describes the maximum electrical ratings for the MSC8103.

CAUTION

This device contains circuitry protecting against damage due to

high static voltage or electrical fields; however, normal precautions

should be taken to avoid exceeding maximum voltage ratings.

Reliability is enhanced if unused inputs are tied to an appropriate

logic voltage level (for example, either GND or VCC).

Table 2-1.

Absolute Maximum Ratings2

Rating

Symbol

Value

Unit

Core supply voltage3

VDD

–0.2 to 1.7

PLL supply voltage3

VCCSYN

–0.2 to 1.7

I/O supply voltage3

VDDH

–0.2 to 3.6

Input voltage3

VIN

(GND – 0.2) to 3.6

Maximum operating temperature range4

–40 to 120

°C

Storage temperature range

TSTG

–55 to +150

°C

Notes:

Functional operating conditions are given in Table 2-2.

Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the listed limits may affect device reliability or cause permanent damage.

The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on reset. In

turn, VDDH can exceed VDD/VCCSYN by more than 3.3 V during power-on reset, but for no more than 100 ms. VDDH should not

exceed VDD/VCCSYN by more than 2.1 V during normal operation. VDD/VCCSYN must not exceed VDDH by more than 0.4 V at

any time, including during power-on reset. See Section 4.2,

Electrical Design Considerations, on page 4-1 for more

information.

Section 4.1,

Thermal Design Considerations, on page 4-1 includes a formula for computing the chip junction temperature

(TJ).

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