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MSC8103/D 数据表(PDF) 23 Page - Freescale Semiconductor, Inc |
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MSC8103/D 数据表(HTML) 23 Page - Freescale Semiconductor, Inc |
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23 / 104 page  CPM Ports MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor 1-19 PA17 FCC1: RXD7 UTOPIA FCC1: RXD0 MII and HDLC nibble FCC1: RXD HDLC serial and transparent Input Input Input FCC1: UTOPIA Receive Data Bit 7. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. FCC1: MII and HDLC Nibble Receive Data Bit 0 RXD[3–0] is supported by MII and HDLC nibble mode in FCC1. RXD0 is the least significant bit. FCC1: HDLC Serial and Transparent Receive Data Bit This is the single receive data bit supported by HDLC and transparent modes. PA16 FCC1: RXD6 UTOPIA FCC1: RXD1 MII and HDLC nibble Input Input FCC1: UTOPIA Receive Data Bit 6. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. This is bit 6 of the receive data. RXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. FCC1: MII and HDLC Nibble Receive Data Bit 1 This is bit 1 of the receive nibble data. RXD3 is the most significant bit. PA15 FCC1: RXD5 UTOPIA RXD2 MII and HDLC nibble Input Input FCC1: UTOPIA Receive Data Bit 5 The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. This is bit 5 of the receive data. RXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. FCC1: MII and HDLC Nibble Receive Data Bit 2 This is bit 2 of the receive nibble data. RXD3 is the most significant bit. PA14 FCC1: RXD4 UTOPIA FCC1: RXD3 MII and HDLC nibble Input Input FCC1: UTOPIA Receive Data Bit 4. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. FCC1: MII and HDLC Nibble Receive Data Bit 3 RXD3 is the most significant bit of the receive nibble bit. PA13 FCC1: RXD3 UTOPIA SDMA: MSNUM2 Input Output FCC1: UTOPIA Receive Data Bit 3 The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. Module Serial Number Bit 2 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0–4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. Table 1-7. Port A Signals (Continued) Name Dedicated I/O Data Direction Description General- Purpose I/O Peripheral Controller: Dedicated Signal Protocol |
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