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MSC8103/D 数据表(PDF) 46 Page - Freescale Semiconductor, Inc |
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MSC8103/D 数据表(HTML) 46 Page - Freescale Semiconductor, Inc |
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46 / 104 page  MSC8103 Network Digital Signal Processor, Rev. 11 2-6 Freescale Semiconductor Physical and Electrical Specifications Table 2-8. SCMR Field Descriptions Name Bit No. Defaults Description Settings PORESET Hard Reset COREPDF 0–3 Configuration Pins Unaffected Core PLL Pre-Division Factor 0000 CPLL PDF = 1 0001 CPLL PDF = 2 0010 CPLL PDF = 3 0011 CPLL PDF = 4 All other combinations not used. COREMF 4–7 Configuration Pins Unaffected Core Multiplication Factor 0101 CPLL MF = 10 0110 CPLL MF = 12 0111 CPLL MF = 14 All other combinations not used. BUSDF 8–11 Configuration Pins Unaffected 60x-compatible Bus Division Factor 0001 Bus DF = 2 0010 Bus DF = 3 0011 Bus DF = 4 0100 Bus DF = 5 0101 Bus DF = 6 All other combinations not used. CPMDF 12–15 Configuration Pins Unaffected CPM Division Factor 0000 CPM DF = 1 0001 CPM DF = 2 0010 CPM DF = 3 All other combinations not used. SPLLPDF 16–19 Configuration Pins Unaffected SPLL Pre-Division Factor 0000 SPLL PDF = 1 0001 SPLL PDF = 2 0010 SPLL PDF = 3 0011 SPLL PDF = 4 0100 SPLL PDF = 5 0101 SPLL PDF = 6 All other combinations not used SPLLMF 20–23 Configuration Pins Unaffected SPLL Multiplication Factor 0101 SPLL MF = 10 0110 SPLL MF = 12 0111 SPLL MF = 14 1000 SPLL MF = 16 1001 SPLL MF = 18 1010 SPLL MF = 20 1011 SPLL MF = 22 1100 SPLL MF = 24 1101 SPLL MF = 26 1110 SPLL MF = 28 1111 SPLL MF = 30 All other combinations not used — 24 —— Reserved DLLDIS 25 Configuration Pins Unaffected DLL Disable 0 DLL operation is enabled 1 DLL is disabled — 26–27 —— Reserved COREDF 28–31 Configuration Pins Unaffected Core Division Factor 0000 CORE DF = 1 0001 CORE DF = 2 0010 CORE DF = 3 0011 CORE DF = 4 0100 CORE DF = 5 0101 CORE DF = 6 All other combinations not used. |
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