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MSC8103/D 数据表(PDF) 27 Page - Freescale Semiconductor, Inc |
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MSC8103/D 数据表(HTML) 27 Page - Freescale Semiconductor, Inc |
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27 / 104 page  CPM Ports MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor 1-23 PB23 FCC2: TXD1 MII and HDLC nibble SI1 TDMA1: L1RXD2 TDM nibble SI2 TDMD2: L1TXD TDM serial Output Input Output FCC2: MII and HDLC Nibble: Transmit Data Bit 1 TXD1 is bit 1 of the transmit data nibble. Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 2 L1RXD2 is bit 2 of the receive data nibble. Time-Division Multiplexing D2: Layer 1 Transmit Data TDMA1 transmits serial data out of L1TXD. PB22 FCC2: TXD0 MII and HDLC nibble FCC2: TXD HDLC serial and transparent SI1 TDMA1: L1RXD1 TDM nibble SI2 TDMD2: L1RXD TDM serial Output Output Input Input FCC2: MII and HDLC Nibble Transmit Data Bit 0 TXD0 is bit 0 and the least significant bit of the transmit data nibble. FCC2: HDLC Serial and Transparent Transmit Data Serial data is transmitted via TXD. Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 1 L1RXD1 is bit 1 of the receive data nibble. Time-Division Multiplexing D2: Layer 1 Receive Data Serial data is received via L1RXD. PB21 FCC2: RXD0 MII and HDLC nibble FCC2: RXD HDLC serial and transparent SI1 TDMA1: L1TXD2 TDM nibble SI2 TDMD2: L1TSYNC TDM serial Input Input Output Input FCC2: MII and HDLC Nibble Receive Data Bit 0 RXD0 is bit 0 and the least significant bit of the receive data nibble. FCC2: HDLC Serial and Transparent Receive Data Serial data is received via RXD. Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 2 L1TXD2 is bit 2 of the transmit data nibble. Time-Division Multiplexing D2: Layer 1 Transmit Synchronize Data The synchronizing signal for the transmit channel. See the Serial Interface with Time-Slot Assigner chapter in the MSC8103 Reference Manual. PB20 FCC2: RXD1 MII and HDLC nibble SI1 TDMA1: L1TXD1 TDM nibble SI2 TDMD2: L1RSYNC TDM serial Input Output Input FCC2: MII and HDLC Nibble: Receive Data Bit 1 RXD1 is bit 1 of the receive data nibble. Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 1 L1TXD1 is bit 1 of the transmit data nibble. Time-Division Multiplexing D2: Layer 1 Receive Synchronize Data The synchronizing signal for the receive channel. PB19 FCC2: RXD2 MII and HDLC nibble I2C: SDA Input Input/ Output FCC2: MII and HDLC Nibble Receive Data Bit 2 RXD2 is bit 2 of the receive data nibble. I2C: Inter-Integrated Circuit Serial Data The I2C interface comprises two signals: serial data (SDA) and serial clock (SDA). The I2C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board. Clock rates run up to 520 kHz@25 MHz system clock. Table 1-8. Port B Signals (Continued) Name Dedicated I/O Data Direction Description General- Purpose I/O Peripheral Controller: Dedicated I/O Protocol |
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