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ST18952 数据表(PDF) 8 Page - STMicroelectronics |
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ST18952 数据表(HTML) 8 Page - STMicroelectronics |
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8 / 67 page  8/66 ST18952 Table 2.9 JTAG IEEE 1149.1 test access port (5 pins) Table 2.10 DMA controller / Serial input/output (8 pins) Pin name Type Description TDI I Test data input. TCK I Test clock. TMS I Test mode select. TDO O Test data output. TRST I Test logic reset (also used for Emulator module). Active low. Pin name Type Description DMARQ0/SRD0 I DMA request 0 or SIO0 Receive data DMARQ1/SCK0 I/O DMA request 1 or SIO0 Data clock DMARQ2/SRD1 I DMA request 2 or SIO1 Receive data DMARQ3/SCK1 I/O DMA request 3 or SIO1 Data clock DMACK0/STD0 O DMA acknowledge 0 or SIO0 Transmit data DMACK1/SFS0 I/O DMA acknowledge 1 or SIO0 Frame synchronizer DMACK2/STD1 O DMA acknowledge 2 or SIO1 Transmit data DMACK3/SFS1 I/O DMA acknowledge 3 or SIO1 Frame synchronizer |
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