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ST18952

Timers

There are two timer (TIM) units on the ST18952. The timers enable interrupts to be generated

after predefined periods of time.

Each timer has the following features:

• 16 bits linear timer / 4 bits exponential prescaler

• counting between 16 bits “start value” and 16 bits “end value”

• counting period between 2 cycles and 232 cycles (50ns to 107s for a 40 MHz

D950). Note, 1 cycle = 2 MCLK periods.

• 1 maskable interrupt request

• external counting clock input

• programmable functions:

•

external / internal clock

•

up / down counting

•

continue / stop modes

•

interrupt enable

When bit 4 of the PICR system register (see Table ) is set to ‘1’, TIM0 interrupt request output

is connected to the ITRQ4 input of the interrupt controller. When bit 5 of the PICR register is

set to ‘1’, TIM1 interrupt request output is connected to the ITRQ5 input of the interrupt

controller. Refer to Chapter 8 for full details on the interrupt controller. After reset, the timers

interrupt outputs are not connected.

Setting the timer enable (TEN) bit of the timer control (TCR) register to ‘1’ starts the timer.

9.1

Timer registers

TCR0-1: Timer control register

The timer control register (TCR) contains timer control information.

(Address = 0058/005C, Reset value = 0000 h, Read/Write)

9876

3210

(0)

TFP(3:0)

ITCM TIE

TCS

TLE

TUD TEN

Bit

Function

TEN

Timer enable (bit 0)

•

When TEN = ‘0’, the TIM is disabled.

•

When TEN = ‘1’, the TIM is started.

Note: the timer must be disabled before the timer registers are configured, otherwise its

behavior is not guaranteed. Once configured it can be enabled.

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