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ST18952 数据表(PDF) 47 Page - STMicroelectronics |
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ST18952 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 67 page ![]() 47/66 ST18952 • Control logic for instruction execution through the PC-board emulator control. Figure 14.1 Emulation block diagram The emulation controller interface (see Table 2.8 and Table 2.9 on page 8) include pins of different types: • ERQ, IDLE and SNAP are used by the emulator tools. • HALTACK indicates that the processor is halted in emulation mode. • AIEBP, AXEBP and AYEBP may be used to set additional conditions for break- point validation on the respective IA/XA/YA buses. BP registers Comparators XA / YA XD / YD IA Control Registers Control Logic PC trace ERQ, IDLE, SNAP RD/WR D950 TAP IA |
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