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ST18952 数据表(PDF) 53 Page - STMicroelectronics |
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ST18952 数据表(HTML) 53 Page - STMicroelectronics |
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53 / 67 page ![]() 53/66 ST18952 Instruction bus electrical characteristics Figure 15.5 Instruction bus timing diagram Table 15.7 Instruction bus timing data No Parameter Min (ns) Typ (ns) Max (ns) t0 Master clock cycle time 7.5 t27 IAE valid delay 1.9 t28 IAE hold time 1.1 t29 IBSE low delay 0.3 t30 IBSE high delay 0.0 t31 IDE high to lo Z delay tbd t32 IDE valid delay tbd t33 IDE hold time 1.2 t34 IWRE low delay t0/2 + 1.6 t35 IWRE high delay 0.6 t36 IDE setup 5.8 t37 IDE hold -4.5 t38 IRDE low delay t0/2 + 0.5 t39 IRDE high delay 0.6 INCYCLE t0 t27 MCLK IAE IBSE IDE IWRE IDE IRDE XX X X t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 CLKOUT |
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