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ST18952 数据表(PDF) 55 Page - STMicroelectronics |
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ST18952 数据表(HTML) 55 Page - STMicroelectronics |
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55 / 67 page ![]() 55/66 ST18952 Y-data bus electrical characteristics Figure 15.7 Y-data bus timing diagram Table 15.9 Y-data bus timing data No Parameter MIN (ns) Typ (ns) Max (ns) t0 Master clock cycle time 7.5 t53 YAE_SA valid delay 3.5 t54 YAE_SA hold time 2.6 t55 YBSE low delay 0.1 t56 YBSE high delay 0.3 t57 YDE_SD high to lo Z delay tbd t58 YDE_SD valid delay t0+3.5 t59 YDE_SD hold time 0.5 t60 YWRE low delay t0+1.7 t61 YWRE high delay 0.5 t62 YDE_SD setup 7.9 t63 YDE_SD hold -5.2 t64 YRDE low delay t0+1.2 t65 YRDE high delay 0.6 INCYCLE t0 t53 MCLK YAE_SA YBSE YDE_SD YWRE YDE_SD YRDE XX X X t54 t55 t56 t57 t58 t59 t60 t61 t62 t63 t64 t65 CLKOUT |
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