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ST18952 数据表(PDF) 54 Page - STMicroelectronics |
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ST18952 数据表(HTML) 54 Page - STMicroelectronics |
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54 / 67 page  54/66 ST18952 X-data bus electrical characteristics Figure 15.6 X-data bus timing diagram Table 15.8 X-data bus timing data No Parameter Min (ns) Typ (ns) Max (ns) t0 Master clock cycle time 7.5 t40 EA_XAE valid delay t0+3.7 t41 EA_XAE hold time 2.7 t42 XBSE low delay 0.1 t43 XBSE high delay -0.2 t44 ED_XDE high to low Z delay tbd t45 ED_XDE valid delay t0+3.9 t46 ED_XDE hold time 0.3 t47 XWRE_EXWR low delay t0+2.7 t48 XWRE_EXWR high delay 0.4 t49 ED_XDE setup 6.5 t50 ED_XDE hold -5.0 t51 XRDE_EXRD low delay t0+2.6 t52 XRDE_EXRD high delay -0.7 INCYCLE t0 t40 MCLK EA_XAE XBSE ED_XDE XWRE_EXWR ED_XDE XRDE_EXRD XX X X t41 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 CLKOUT |
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