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ST18952 数据表(PDF) 56 Page - STMicroelectronics |
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ST18952 数据表(HTML) 56 Page - STMicroelectronics |
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56 / 67 page ![]() 56/66 ST18952 Bus switch electrical characteristics (Intel mode) Figure 15.8 Bus switch timing diagram (intel mode) Table 15.10 Y-data bus switch timing data No Parameter Min (ns) Typ (ns) Max (ns) t0 Master clock cycle time 7.5 t66 EA_XAE valid delay 4.4 t67 EA_XAE hold time 3.3 t68 ED_XDE high to lo Z delay tbd t69 ED_XDE valid delay t0+2.4 t70 ED_XDE hold time 1.6 t71 EI/X/YWR low delay t0+2.3 t72 EI/X/YWR high delay 1.9 t73 ED_XDE setup 7.1 t74 ED_XDE hold -5.8 t75 EI/X/YRD low delay t0+2.1 t76 EI/X/YRD high delay -1.5 t66 EA_XAE ED_XDE EI/X/YWR ED_XDE EI/X/YRD XX X t67 t68 t69 t70 t71 t72 t73 t74 t75 t76 X Data_out INCYCLE t0 MCLK CLKOUT |
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