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ST18952 数据表(PDF) 41 Page - STMicroelectronics

部件名 ST18952
功能描述  DIGITAL SIGNAL PROCESSOR DSP CHIP
PDF  67 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST18952 数据表(HTML) 41 Page - STMicroelectronics

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ST18952
STDR: SIO Transmit data register
(SIO0 address = 0060h reset value = 0000h, write only)
(SIO1 address = 00E0h reset value = 0000h, write only)
SRDR: SIO Receive data register
(SIO0 address = 0061h, reset value = xxxxh, read only)
(SIO1 address = 00E1h, reset value = xxxxh, read only)
15
14
13
12
11
10
9876
54
3210
STD
15
STD
14
STD
13
STD
12
STD
11
STD
10
STD
9
STD
8
STD
7
STD
6
STD
5
STD
4
STD
3
STD
2
STD
1
STD
0
Bit
Function
STD(15:0)
SIO Transmit data (STD(15) = msb)
•
STD contains the data to be transferred to the Transmit Shift register at the beginning
of the next sub-frame or time slot. The data is transmitted msb first.
•
When 8-bit data format (SCR/SWL = ‘1’) is used, the byte must be left justified (written
on bits 7 to 0, bits 15 to 8 are ignored). The msb is bit 7.
15
14
13
12
11
10
9876
54
3210
SRD
15
SRD
14
SRD
13
SRD
12
SRD
11
SRD
10
SRD
9
SRD
8
SRD
7
SRD
6
SRD
5
SRD
4
SRD
3
SRD
2
SRD
1
SRD
0
Bit
Function
SRD(15:0)
SIO Receive data (SRD(15) = msb)
•
SRD contains the data transferred from the Receive Shift register at the end of the
last sub-frame or time slot. The data is right justified (msb = bit 15).
•
When 8-bit data format (SCR/SWL = ‘1’) is used, the byte is left justified (significative
on bits 7 to 0, bits 15 to 8 are ignored). The msb is bit 7.



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