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ST18952 数据表(PDF) 49 Page - STMicroelectronics |
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ST18952 数据表(HTML) 49 Page - STMicroelectronics |
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49 / 67 page ![]() 49/66 ST18952 15.3 AC Characteristics The following timings are based on simulations and may change when full characterisation is completed. Clocks electrical characteristics Figure 15.1 Clock timing diagram Table 15.3 Clock timing data No Parameter Min (ns) Typ (ns) Max (ns) t0 Master clock cycle time 7.5 t3 CLKOUT high delay 4.0 t4 CLKOUT low delay 3.3 t5 INCYCLE high delay -0.1 t6 INCYCLE low delay -0.5 t0 MCLK CLKOUT INCYCLE t3 t5 t4 t6 |
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