ST18952 datasheet(22/67 Pages) STMICROELECTRONICS

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ST18952

7.1

DMA operation

The DMA controller interface contains four independent channels allowing data transfer on I-

memory space and simultaneous data transfer on X and Y-memory spaces. When requests

to transfer data on the same bus occur at the same time on different channels, the requests

are concatenated to be acknowledged during the same transfer according to fixed priority.

Channel 0 has the highest priority ranging to channel 3 with the lowest priority.

The DMA transfer is based on a DSP cycle stealing operation:

• DMA controller generates a ‘hold request’.

• The core sends back a ‘hold acknowledge’ to the DMA controller and enters

the hold state (bus released).

• The DMA controller manages the transfer and enters its idle state at the end of

the transfer, until reception of a new DMA request. The ‘hold request’ signal is

removed.

The data transfer duration is n+2 cycles, split into:

• One cycle inserted at the beginning of the transfer when bus controls are

released by the D950Core, n cycles for the number of data words to be trans-

ferred.

• Another cycle is inserted at the end of the transfer when bus controls are

released by the DMA controller.

Single or block data can be transferred. The DMA request signal (DMARQ) can be either edge

(single) or level (block) sensitive. Data blocks can be transferred one data at a time using an

edge sensitive request signal.

A double buffering mechanism is available to deal with data blocks requiring the allocation of

2N addresses for the transfer of an N data block.

An interrupt can be used to warn AS-DSP that a predefined number of data have been

transferred and are ready to be processed. Interrupt requests are sent from the DMA controller

to the interrupt controller. The selected channels must be edge sensitive and the user has to

define the proper priority.

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