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ST18952

Interrupt Controller

The interrupt controller (ITC) can manage up to eight external interrupts. The interrupt

controller has the following features:

• 8 independent interrupt sources, each one associated with:

•

16-bit programmable interrupt vector - provides the address of the first instruction

of the interrupt routine associated with the source.

•

mask bit, enabling each source to be activated or deactivated

•

sensitivity bit (edge/level)

•

2-bit programmable priority level

•

‘pending interrupt’ flag - displays the source waiting for service. This flag is writ-

able to allow a software interrupt capability.

• Interrupt processing whenever its priority level is higher than the current priority

level.

• Nested of up to 4 interrupts(the stack content is accessible in read or write).

Figure 8.1

D950Core interrupt controller

The interrupt controller ITRQ inputs can be connected to external interrupt requests or to

internal peripheral requests, this is dependent on the setting of the port/interrupt control (PICR)

system register, see Table on page 43 for details. The interrupt controller receives interrupt

D950Core

INTERRUPT

CONTROLLER

PERIPHERAL

ITRQ1

ITACK

EOI

YWR

RESET

CLK

INCYCLE

ITACK

YWR

YRD

EOI

ITRQ0

ITRQ2

ITRQ3

ITRQ4

ITRQ5

ITRQ6

ITRQ7

AS-DSP

VR02020C

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