ST18952 datasheet(27/67 Pages) STMICROELECTRONICS

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ST18952

requests from primary inputs P_ITRQ0-7 on its inputs ITRQ0-7 when bit 0-7 of the PICR

request output. Each input can be programmed independently.

8.1

Interrupt controller registers

The interrupt controller interface is controlled by status and control registers mapped into the

Y-memory space. Status registers are not write-protected.

IVO0-7: Interrupt vector0-7 address registers

The IVO0-7 registers (one per external interrupt) contain the first address of the interrupt

routine and are associated with the respective interrupt input ITRQ0-7. The register content of

the interrupt under service is provided on the YD bus during the cycle following the ITACK

falling edge.

(Address = 0020-0027, No reset value, Read/Write)

ICR: Interrupt control register

The ICR register displays the current priority level and up to four stacked priority levels.

(Address = 0028, Reset = 000Bh, Read/Write))

9876

3210

IVi 15 IVi 14 IVi 13 IVi 12 IVi 11 IVi 10

IVi 9

IVi 8

IVi 7

IVi 6

IVi 5

IVi 4

IVi 3

IVi 2

IVi 1

IVi 0

SPL4 (2:0)

SPL3 (2:0)

SPL2 (2:0)

SPL1 (2:0)

CPL (2:0)

Bit

Function

CPL

Current priority level (-1, 0, 1, 2 or 3) (default is 011)

Empty stack flag

0: stack is used

1: stack is not used (default)

SPL1

3-bit 1st stacked priority level

SPL2

3-bit 2nd stacked priority level

SPL3

3-bit 3rd stacked priority level

SPL4

3-bit 4th stacked priority level

ST18952 数据表(PDF) 27 Page - STMicroelectronics

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