ST18952 datasheet(24/67 Pages) STMICROELECTRONICS

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ST18952

DGC: General control register

Three bits are dedicated for each DMA channel (bits 0 to 2 to channel 0, bits 4 to 6 to channel

1, bits 8 to 10 to channel 2, bits 12 to 14 to channel 3).

(Address = 0040, Reset = 0000h, Read/Write).

DAIC: Address/interrupt control register

Four bits are dedicated for each DMA channel (bits 0 to 3 to channel 0, bits 4 to 7 to channel

1, bits 8 to 11 to channel 2, bits 12 to 15 to channel 3).

(Address = 0042, Reset = 0000h, Read/Write)

DRW3 DBC1 DBC0

DRW2 DBC1 DBC0

DRW1 DBC1 DBC0

DRW0 DBC1 DBC0

Bit

Function

DBC1/DBC0

Bus choice for data transfer

00: X-bus (default)

01: Y-bus

10: I-bus

11: reserved

DRWi

Data transfer direction

0: Write access (default)

1: Read access

DAI3

DLA3

DIP3

DIE3

DAI2

DLA2

DIP2

DIE2

DAI1

DLA1

DIP1

DIE1

DAI0

DLA0

DIP0

DIE0

Bit

Function

DIEi

Enable interrupt

Interrupt request output associated to channel i is masked (default)

Interrupt request output associated to channel i is not masked

DIPi

Interrupt pending

No pending interrupt on channel i (default)

Pending interrupt on channel i (enabled if DIP_ENA input is high)

DLAi:

Load address

DCAi content incremented after each data transfer (default)

DCAi content loaded with DIA content if DCCi value is 0,

or DCAi content incremented if DCCi value is not equal to 0

DAIi

Address increment

DCAi content unchanged (default)

DCAi content modified according to DLAi state

ST18952 数据表(PDF) 24 Page - STMicroelectronics

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