ST18952 datasheet(21/67 Pages) STMICROELECTRONICS

21 / 67 page

21/66

ST18952

DMA Controller

The DMA controller manages data transfer between memories and external peripherals and

has the following features:

• four independent DMA channels

• transfers on X / Y / I spaces (simultaneous transfers on X and Y spaces)

• cycle stealing operation:

•

3 cycles for a single data transfer (+1cycle for transfers on I space)

•

(n+2) cycles for an n-data block transfer (+1cycle for transfers on I space)

• each channel has:

•

3 signals: request (DMARQ), acknowledge (DMACK), interrupt request (DIT)

•

4x16 bit registers for block transfer facilities

• fixed priority between the four channels (highest channel 0, lowest channel 3)

The DMA controller DMARQ0-3 inputs and DMACK0-3 outputs are available as primary

inputs, in the case of SIO inhibition. This is set by the DMAR register (see ”DMAR: DMA

management register” on page 44).

Figure 7.1

DMA controller

D950Core

INTERR UPT

CONTROLLER

PERIPHERAL

RESET

AS-D SP

HOLD

HOLDACK

INCY CLE

DMA CONTROLLER PERIPHERAL

DMARQ0

DMARQ1

DMARQ2

DMARQ3

DMACK0

DMACK1

DMACK2

DMACK3

DTACK

DIP_ENA

XA XD

IRD

IWR

IBS

XR D

XW R

XB S

YRD

YWR

YBS

DIT 0

DIT1

DIT2

DIT3

DIT_AND

CLK

DMA_CLK

ST18952 数据表(PDF) 21 Page - STMicroelectronics

ST18952 数据表(HTML) 21 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

数据表下载