ST18952 datasheet(14/67 Pages) STMICROELECTRONICS

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ST18952

4.1

D950Core registers

PCDR

The Port Control Direction register defines the data direction of each port pin. After reset,

PCDR default value is 0 (Port pins are configured as inputs)

PCSR

The Port Control Sensitivity register defines sensitivity of each port pin. After reset, PCSR

default value is 0 (Port pins are configured as level-sensitive).

Function

Modulo base address for X-memory space

Modulo maximum address for X-memory space

Modulo base address for Y-memory space

Modulo maximum address for Y-memory space

POR

Port Output Register - 8LSB are significant, 8MSB are undefined when reading

PIR

Port Input Register

PCDR

Port Control Direction Register

PCSR

Port Control Sensitivity Register

9876543210

--------

P7D

P6D

P5D

P4D

P3D

P2D

P1D

P0D

Bit

Function

PiD

Port pin direction

0: Input port pin (def.)

1: Output port pin

Bits 8 - 15

RESERVED (read: undefined, write: don’t care)

9876543210

--------

P7S

P6S

P5S

P4S

P3S

P2S

P1S

P0S

Bit

Function

PiS

Port pin sensitivity

0: Level sensitive (def.)

1: Edge sensitive

Bits 8 - 15

RESERVED (read: undefined, write: don’t care)

ST18952 数据表(PDF) 14 Page - STMicroelectronics

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