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ST18952 数据表(PDF) 45 Page - STMicroelectronics |
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ST18952 数据表(HTML) 45 Page - STMicroelectronics |
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45 / 67 page  45/66 ST18952 Note: Use of an external DMA controller is possible. In this case, only exchanges between external peripherals and external memories are allowed. All direct extension buses are isolated. 12.2 Clocks A 27 MHz crystal can be used with the on-chip oscillator and PLL to provide the D950 clock input. The PLL module multiplies the oscillator frequency by a factor of 10 and generates a 270 MHz signal. A programmable divisor is connected to the PLL output to generate the D950 clock input. The division range is 2 to 256 and can be programmed by writing to the CMR clock management system register. CMR: Clock management register (Address = 0048h, Reset = 0000h, Read/Write) The oscillator and PLL can be bypassed by setting the CLK_MODE pin to ‘1’. In this case the D950 CLKIN input receives the clock signal directly from the MCLK input. 15 14 13 12 11 10 9 87654 321 0 Reserved D2 D1 D0 D2 D1 D0 Division factor Output clock frequency 0 0 0 2 135 MHz 0 0 1 4 67.5 MHz 0 1 0 8 33.74 MHz 0 1 1 16 16.88 MHz 1 0 0 32 8.44 MHz 1 0 1 64 4.22 MHz 1 1 0 128 2.11 MHz 1 1 1 256 1.05 MHz |
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