ST18952 datasheet(39/67 Pages) STMICROELECTRONICS

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ST18952

SFR: SIO Frequency register

(SIO0 address = 0063h, reset value = 0000h, read/write)

(SIO1 address = 00E3 h, reset value = 0000h, read/write)

SFR Writes must be made when the SEN bit of the SER register is ‘0’ (SIO disabled)

SER: SIO Enable register

(SIO0 address = 0064h, reset value = 0000h, read/write)

(SIO1 address = 00E4 h, reset value = 0000h, read/write)

9876

3210

(0)

SFD(2:0)

SFP

Bit

Function

SFP

SIO Frequency prescaler

•

When the SCK clock is generated internally (SCSD bit of the SCR register is set to

‘1’), it is derived from the MCLK clock input by first prescaling MCLK by 1 (SFP = ‘0’

reset value) or by 3 (SFP = ‘1’).

SFD(2:0)

SIO Frequency divider (bits 3-1; SFD(2) = msb)

•

When the SCK clock is generated internally (SCR/SCSD = ‘1’), it is derived from the

MCLK clock input by second dividing MCLK by 2(1 + SFD).

SFD = “0”

divided by 2 (reset value)

SFD = “1”

divided by 4

SFD = “2”

divided by 8

...

SFD = “7”

divided by 256

Bits 5 and 4

Reserved and must be written as ‘0’

Bits 15 to 6

Unused and read as ‘0’

9876

3210

(0)

SEN

Bit

Function

SEN

SIO Enable

•

When SEN = ‘0’, SIO is disabled (reset value). SCR and SFR writes must be made

when SEN = ‘0’.

•

When SEN = ‘1’, the SIO is enabled.

Bits 15 to 1

Unused and read as ‘0’

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