ST18952 datasheet(40/67 Pages) STMICROELECTRONICS

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ST18952

SSR: SIO Status register

(SIO0 address = 0065h, reset value = 0000 h, read only)

(SIO1 address = 00E5h, reset value = 0000 h, read only)

9876

3210

SLRA(7:0)

SCWN(2:0)

SROV SRDF STUN STDE

Bit

Function

STDE

SIO Transmit data empty

•

STDE is set when the content of the STDR Data register is transferred into the Trans-

mit Shift register signalling that the STDR Data register is ready to be receive the next

word to be transmitted.

•

If the STIE enable bit is set, an interrupt request occurs on the STI output (STI is low

for 1 MCLK cycle) when STDE is set.

STUN

SIO Transmit underrun

•

STUN is set when the Transmit Shift register is empty and the STDR Data register

has not been filled by the DSP.

•

If another frame syncho occurs, the content of the STDR Data register is transferred

again into the Transmit Shift register and the previous word is re-transmitted.

SRDF

SIO Receive data full

•

SRDF is set when the content of the Receive Shift register has been transferred into

the SRDR Data register, signalling a new word receive. The SRDR Data register is

ready to be read by the DSP.

•

If the SRIE enable bit is set, an interrupt request occurs on the SRI output (SRI is low

for 1 MCLK cycle) when SRDF is set.

SROV

SIO Receive overrun

•

SROV is set when the Receive Shift register is ready to be transferred into the SRDR

Data register, which has not been read by the DSP.

•

If another frame syncho occurs, the content of the Receive Shift register is transferred

into the SRDR Data register and the previous content of SRDR is lost.

Bit 4

Unused and read as ‘0’

SCWN(2:0)

SIO Current word number (SCWN(2) = msb)

•

In normal and microwire modes, SCWN contains the current word number value

since the last frame synchro. In tdm mode, SCWN determines the current slot number

value since the last frame synchro.

SCWN = 0 -> 1st sub-frame / time slot

SCWN = 1 -> 2nd sub-frame / time slot

...

SCWN = 7 -> 8th sub-frame / time slot

SLRA(7:0)

SIO Last received address (bits 15-8)

Must write 0.

ST18952 数据表(PDF) 40 Page - STMicroelectronics

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