T89C51AC2-RLSI-M datasheet(64/117 Pages) ATMEL

64 / 117 page

Draft.A - March 30, 2001

Preview - Confidential

T89C51AC2

13. Timer 2

13.1. Introduction

The T89C51AC2 timer 2 is compatible with timer 2 in the 80C52.

It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade-

connected. It is controlled by T2CON register (See Table 55) and T2MOD register (See Table 56). Timer 2 operation

is similar to Timer 0 and Timer 1. C/T2 selects FOSC/6 (timer operation) or external pin T2 (counter operation)

as timer register input. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 includes the following enhancements:

• Auto-reload mode (up or down counter)

• Programmable clock-output

13.2. Auto-Reload Mode

The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. This feature is

controlled by the DCEN bit in T2MOD register (See Table 56). Setting the DCEN bit enables timer 2 to count up

or down as shown in Figure 53. In this mode the T2EX pin controls the counting direction.

When T2EX is high, timer 2 up-counts. Timer overflow occurs at FFFFh which sets the TF2 flag and generates

an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded

into the timer registers TH2 and TL2.

When T2EX is low, timer 2 down-counts. Timer underflow occurs when the count in the timer registers TH2 and

TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh

into the timer registers.

The EXF2 bit toggles when timer 2 overflow or underflow, depending on the direction of the count. EXF2 does

not generate an interrupt. This bit can be used to provide 17-bit resolution.

T89C51AC2-RLSI-M 数据表(PDF) 64 Page - ATMEL Corporation