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T89C51AC2-RLSI-M 数据表(PDF) 90 Page - ATMEL Corporation |
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T89C51AC2-RLSI-M 数据表(HTML) 90 Page - ATMEL Corporation |
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90 / 117 page ![]() 90 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 16.6. Clock Selection The maximum clock frequency for ADC is 700KHz. A prescaler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency. Figure 79. A/D Converter clock 16.7. ADC Standby Mode When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode the power dissipation is about 1uW. Prescaler ADCLK A/D Converter conversion clock fADC CPU CLOCK CPU Core Clock Symbol ÷ 2 |
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