T89C51AC2-RLSI-M datasheet(6/117 Pages) ATMEL

6 / 117 page

Draft.A - March 30, 2001

Preview - Confidential

T89C51AC2

4.1. I/O Configurations

Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch"

signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched

Q uotput onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port

data instructions activate the "read latch" signal while others activate the "read pin" signal. Latch instructions are

referred to as Read-Modify-Write instructions. Each I/O line may be independently programmed as input or output.

4.2. Port 1, Port 3 and Port 4

Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external source can pull the pin

low. Each Port pin can be configured either forgeneral-purpose I/O or for its alternate input output function.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x=1,3 or 4). To use

a pin for general purpose input, set the bit in the Px register. This turns off the output FET drive.

To configure a pin for its alternate function, set the bit in the Px register. When the latch is set, the "alternate

output function" signal controls the output level (see Figure 1). The operation of Ports 1, 3 and 4 is discussed

further in "quasi-Bidirectional Port Operation" paragraph.

NOTE:

1. The internal pull-up can be disabled on P1 when analog function is selected.

Figure 1. Port 1, Port 3 and Port 4 Structure

4.3. Port 0 and Port2

Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port 0, shown in Figure 2,

differs from the other Ports in not having internal pull-ups. Figure 3 shows the structure of Port 2. An external

source can pull a Port 2 pin low.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x=0 or 2). To use

a pin for general purpose input, set the bit in the Px register to turn off the output driver FET.

P1.X

LATCH

INTERNAL

WRITE

LATCH

READ

LATCH

P1.x

P3.X

P4.X

ALTERNATE

OUTPUT

FUNCTION

VCC

INTERNAL

PULL-UP (1)

ALTERNATE

INPUT

FUNCTION

P3.x

P4.x

BUS

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