T89C51AC2-RLSI-M datasheet(31/117 Pages) ATMEL

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Draft.A - March 30, 2001

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T89C51AC2

8.2. Internal Space

8.2.1. Lower 128 Bytes RAM

The lower 128 bytes of RAM (see Figure 17) are accessible from address 00h to 7Fh using direct or indirect

addressing modes. The lowest 32 bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1

in PSW register (see Figure 23) select which bank is in use according to Table 15. This allows more efficient use

of code space, since register instructions are shorter than instructions that use direct addressing, and can be used

for context switching in interrupt service routines.

Table 15. Register Bank Selection

The next 16 bytes above the register banks form a block of bit-addressable memory space. The C51 instruction

set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by

these instructions. The bit addresses in this area are 00h to 7Fh.

Figure 18. Lower 128 bytes Internal RAM Organization

8.2.2. Upper 128 Bytes RAM

The upper 128 bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode.

8.2.3. Expanded RAM

The on-chip 1024 bytes of expanded RAM (ERAM) are accessible from address 0000h to 03FFh using indirect

addressing mode through MOVX instructions. In this address range, the bit EXTRAM in AUXR register is used

to select the ERAM (default) or the XRAM. As shown in Figure 17 when EXTRAM= 0, the ERAM is selected

and when EXTRAM= 1, the XRAM is selected.

Caution:

Lower 128 bytes RAM, Upper 128 bytes RAM, and expanded RAM are made of volatile memory cells. This means that the RAM content is

indeterminate after power-up and must then be initialized properly.

RS1

RS0

Description

Bit-Addressable Space

4 Banks of

8 Registers

R0-R7

30h

7Fh

(Bit Addresses 0-7Fh)

20h

2Fh

18h

1Fh

10h

17h

08h

0Fh

00h

07h

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