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T89C51AC2-RLSI-M 数据表(PDF) 32 Page - ATMEL Corporation

部件名 T89C51AC2-RLSI-M
功能描述  8-bit MCU with 32K bytes Flash, 10 bits A/D and EEPROM
PDF  117 Pages
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制造商  ATMEL [ATMEL Corporation]
网页  http://www.atmel.com
标志 ATMEL - ATMEL Corporation

T89C51AC2-RLSI-M 数据表(HTML) 32 Page - ATMEL Corporation

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Draft.A - March 30, 2001
Preview - Confidential
T89C51AC2
8.3. External Space
8.3.1. Memory Interface
The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals
(RD#, WR#, and ALE).
Figure 19 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8.
Data D7:0 is multiplexed with A7:0 on P0. Table 16 describes the external memory interface signals.
Figure 19. External Data Memory Interface Structure
Table 16. External Data Memory Interface Signals
8.3.2. External Bus Cycles
This section describes the bus cycles the T89C51AC2 executes to read (see Figure 20), and write data (see Figure 21)
in the external data memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard
mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode.
Slow peripherals can be accessed by stretching the read and write cycles. This is done using the M0 bit in AUXR
register. Setting this bit changes the width of the RD# and WR# signals from 3 to 15 CPU clock periods.
Signal Name
Type
Description
Alternative Function
A15:8
O
Address Lines
Upper address lines for the external bus.
P2.7:0
AD7:0
I/O
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
P0.7:0
ALE
O
Address Latch Enable
ALE signals indicates that valid address information are available on lines AD7:0.
-
RD#
O
Read
Read signal output to external data memory.
P3.7
WR#
O
Write
Write signal output to external memory.
P3.6
RAM
PERIPHERAL
<Generic
P2
P0
AD7:0
A15:8
A7:0
A15:8
D7:0
A7:0
ALE
WR
OE
RD#
WR#
Latch



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