T89C51AC2-RLSI-M datasheet(96/117 Pages) ATMEL

96 / 117 page

Draft.A - March 30, 2001

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T89C51AC2

17.2. Registers

IEN0 (S:A8h)

Interrupt Enable Register

Reset Value: 0000 0000b

bit addressable

Figure 87. IEN0 Register

ET2

ET1

EX1

ET0

EX0

Bit Number Bit Mnemonic

Description

7EA

Enable All interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt

enable bit.

6EC

PCA Interrupt Enable

Clear to disable the PCA interrupt.

Set to enable the PCA interrupt.

ET2

Timer 2 overflow interrupt Enable bit

Clear to disable timer 2 overflow interrupt.

Set to enable timer 2 overflow interrupt.

4ES

Serial port Enable bit

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

ET1

Timer 1 overflow interrupt Enable bit

Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

EX1

External interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

ET0

Timer 0 overflow interrupt Enable bit

Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

EX0

External interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

T89C51AC2-RLSI-M 数据表(PDF) 96 Page - ATMEL Corporation

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