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T89C51AC2-RLSI-M 数据表(PDF) 33 Page - ATMEL Corporation |
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T89C51AC2-RLSI-M 数据表(HTML) 33 Page - ATMEL Corporation |
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33 / 117 page ![]() Draft.A - March 30, 2001 33 Preview - Confidential T89C51AC2 For simplicity, the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing information. For bus cycle timing parameters refer to the Section “AC Characteristics” of the T89C51AC2 datasheet. Figure 20. External Data Read Waveforms Notes: 1. RD# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. 3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH. Figure 21. External Data Write Waveforms Notes: 1. WR# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. 3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH. ALE P0 P2 RD#1 DPL or Ri D7:0 DPH or P22,3 P2 CPU Clock ALE P0 P2 WR#1 DPL or Ri D7:0 P2 CPU Clock DPH or P22,3 |
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