T89C51AC2-RLSI-M datasheet(89/117 Pages) ATMEL

89 / 117 page

Draft.A - March 30, 2001

Preview - Confidential

T89C51AC2

16.4. ADC Converter Operation

A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).

The busy flag ADSST(ADCON.3) is automatically set when an A/D conversion is running. After completion of

the A/D conversion, it is cleared by hardware. This flag can be read only, a write has no effect.

The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and

ADDL, it is cleared by software. If the bit EADC (IEN1.1) is set, an interrupt occur when flag ADEOC is set

(see Figure 80). Clear this flag for re-arming the interrupt.

The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection.

Before Starting Power reduction modes the ADC conversion has to be completed.

Table 21. Selected Analog input

16.5. Voltage Conversion

When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage

equals VAGND, the ADC converts it to 000h. Input voltage between VAREF and VAGND are a straight-line

linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range!

SCH2

SCH1

SCH0

Selected Analog input

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

T89C51AC2-RLSI-M 数据表(PDF) 89 Page - ATMEL Corporation