T89C51AC2-RLSI-M datasheet(38/117 Pages) ATMEL

38 / 117 page

Draft.A - March 30, 2001

Preview - Confidential

T89C51AC2

9. EEPROM data memory

9.1. General description

The 2k byte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM memory space

and is selected by setting control bits in the EECON register.

A read in the EEPROM memory is done with a MOVX instruction.

A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of

all data latches into an EEPROM memory row (programming).

The number of data written on the page may vary from 1 to 128 bytes (the page size). When programming, only

the data written in the column latch is programmed and a ninth bit is used to obtain this feature. This provides

the capability to program the whole memory by bytes, by page or by a number of bytes in a page. Indeed, each

ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing

of the complete EEPROM row.

9.2. Write Data in the column latches

Data is written by byte to the column latches as for an external RAM memory. Out of the 11 address bits of the

data pointer, the 4 MSBs are used for page selection (row) and 7 are used for byte selection. Between two EEPROM

programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4

MSB must no be changed.

The following procedure is used to write to the column latches:

• Set bit EEE of EECON register

• Load DPTR with the address to write

• Store A register with the data to be written

• Execute a MOVX @DPTR, A

• If needed loop the three last instructions until the end of a 128 bytes page

9.3. Programming

The EEPROM programming consists on the following actions:

• writing one or more bytes of one page in the column latches. Normally, all bytes must belong to the same

page; if not, the first page address will be latched and the others discarded.

• launching programming by writing the control sequence (54h followed by A4h) to the EECON register.

• EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the

EEPROM segment is not available for reading.

• The end of programming is indicated by a hardware clear of the EEBUSY flag.

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