T89C51AC2-RLSI-M datasheet(19/117 Pages) ATMEL

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Draft.A - March 30, 2001

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T89C51AC2

Figure 9. External Code Memory Interface Structure

Table 12. External Data Memory Interface Signals

7.2.2. External Bus Cycles

This section describes the bus cycles the T89C51AC2 executes to fetch code (see Figure 10) in the external program/

code memory.

External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard

mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode.(see the clock Section)

For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and do not provide

precise timing information.

Figure 10. External Code Fetch Waveforms

Signal

Name

Type

Description

Alternate

Function

A15:8

Address Lines

Upper address lines for the external bus.

P2.7:0

AD7:0

I/O

Address/Data Lines

Multiplexed lower address lines and data for the external memory.

P0.7:0

ALE

Address Latch Enable

ALE signals indicates that valid address information are available on lines AD7:0.

PSEN#

Program Store Enable Output

This signal is active low during external code fetch or external code read (MOVC instruction).

FLASH

EPROM

T89C51AC2

AD7:0

A15:8

A7:0

A15:8

D7:0

A7:0

ALE

Latch

PSEN#

ALE

PSEN#

PCL

PCH

PCL

D7:0

PCH

D7:0

CPU Clock

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