T89C51AC2-RLSI-M datasheet(52/117 Pages) ATMEL

52 / 117 page

Draft.A - March 30, 2001

Preview - Confidential

T89C51AC2

The software may examine the FE bit after each reception to check for data errors. Once set, only software or a

reset clears the FE bit. Subsequently received frames with valid stop bits cannot clear the FE bit. When the FE

feature is enabled, RI rises on the stop bit instead of the last data bit (See Figure 35. and Figure 36.).

Figure 35. UART Timing in Mode 1

Figure 36. UART Timing in Modes 2 and 3

11.2. Automatic Address Recognition

The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled

(SM2 bit in SCON register is set).

Implemented in the hardware, automatic address recognition enhances the multiprocessor communication feature

by allowing the serial port to examine the address of each incoming command frame. Only when the serial port

recognizes its own address will the receiver set the RI bit in the SCON register to generate an interrupt. This

ensures that the CPU is not interrupted by command frames addressed to other devices.

If necessary, you can enable the automatic address recognition feature in mode 1. In this configuration, the stop

bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the

device’s address and is terminated by a valid stop bit.

To support automatic address recognition, a device is identified by a given address and a broadcast address.

NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON

Data byte

SMOD0=X

Stop

bit

Start

bit

RXD

SMOD0=1

SMOD0=0

Data byte

Ninth

bit

Stop

bit

Start

bit

RXD

SMOD0=1

T89C51AC2-RLSI-M 数据表(PDF) 52 Page - ATMEL Corporation

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