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T89C51AC2-RLSI-M 数据表(PDF) 24 Page - ATMEL Corporation |
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T89C51AC2-RLSI-M 数据表(HTML) 24 Page - ATMEL Corporation |
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24 / 117 page  24 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 7.4.5. Loading the Column Latches Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This provides the capability to program the whole memory by byte, by page or by any number of bytes in a page. When programming is launched, an automatic erase of the locations loaded in the column latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page. The following procedure is used to load the column latches and is summarized in Figure 12: • Map the column latch space by setting FPS bit. • Load the DPTR with the address to load. • Load Accumulator register with the data to load. • Execute the MOVX @DPTR, A instruction. • If needed loop the three last instructions until the page is completely loaded. Figure 12. Column Latches Loading Procedure Column Latches Loading Data Load DPTR= Address ACC= Data Exec: MOVX @DPTR, A Last Byte to load? Column Latches Mapping FPS= 1 Data memory Mapping FPS= 0 |
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