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T89C51AC2-RLSI-M 数据表(PDF) 99 Page - ATMEL Corporation |
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T89C51AC2-RLSI-M 数据表(HTML) 99 Page - ATMEL Corporation |
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99 / 117 page  Draft.A - March 30, 2001 99 Preview - Confidential T89C51AC2 IPL1 (S:F8h) Interrupt Priority Low Register 1 Reset Value: xxxx xx0xb bit addressable Figure 90. IPL1 Register 7 6 5 4 3 2 1 0 - - - - - - PADCL - Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2- Reserved The value read from this bit is indeterminate. Do not set this bit. 1 PADCL ADC Interrupt Priority level less significant bit. Refer to PSPIH for priority level. 0- Reserved The value read from this bit is indeterminate. Do not set this bit. |
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