T89C51AC2-RLSI-M datasheet(92/117 Pages) ATMEL

92 / 117 page

Draft.A - March 30, 2001

Preview - Confidential

T89C51AC2

16.9. Registers

ADCF (S:F6h)

ADC Configuration

Reset Value=0000 0000b

Figure 81. ADCF Register

ADCON (S:F3h)

ADC Control Register

Reset Value=X000 0000b

Figure 82. ADCON Register

CH 7

CH 6

CH 5

CH 4

CH 3

CH 2

CH 1

CH 0

Bit Number

Bit

Mnemonic

Description

7-0

CH 0:7

Channel Configuration

Set to use P1.x as ADC input.

Clear tu use P1.x as standart I/O port.

PSIDLE

ADEN

ADEOC

ADSST

SCH2

SCH1

SCH0

Bit Number Bit Mnemonic

Description

PSIDLE

Pseudo Idle mode (best precision)

Set to put in idle mode during conversion

Clear to converte without idle mode.

ADEN

Enable/Standby Mode

Set to enable ADC

Clear for Standby mode (power dissipation 1 uW).

ADEOC

End Of Conversion

Set by hardware when ADC result is ready to be read. This flag can generate an interrupt.

Must be cleared by software.

ADSST

Start and Status

Set to start an A/D conversion.

Cleared by hardware after completion of the conversion

2-0

SCH2:0

Selection of channel to convert

see Table 21

T89C51AC2-RLSI-M 数据表(PDF) 92 Page - ATMEL Corporation

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