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数据搜索系统，热门电子元器件搜索 |
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T89C51AC2-RLSI-M 数据表(PDF) 82 Page - ATMEL Corporation |
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T89C51AC2-RLSI-M 数据表(HTML) 82 Page - ATMEL Corporation |
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82 / 117 page  82 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 15.8. PCA Registers CMOD (S:D8h) PCA Counter Mode Register Reset Value = 00XX X000b Figure 70. CMOD Register 7 6 5 4 3 2 1 0 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description 7 CIDL PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. 6 WDTE Watchdog Timer Enable Clear to disable Watchdog Timer function on PCA Module 4, Set to enable it. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2 CPS1 EWC Count Pulse Select bits CPS1 CPS0 Clock source 0 0 Internal Clock, FPca/6 0 1 Internal Clock, FPca/2 1 0 Timer 0 overflow 1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4) 1 CPS0 0 ECF Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt. |
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