T89C51AC2-RLSI-M datasheet(5/117 Pages) ATMEL

5 / 117 page

Draft.A - March 30, 2001

Preview - Confidential

T89C51AC2

P3.0:7

I/O

Port 3:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are

pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3

pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the

internal pull-ups.

The output latch corresponding to a secondary function must be programmed to one for that function to

operate (except for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows:

P3.0 / RxD:

Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface

P3.1 / TxD:

Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface

P3.2 / INT0:

External interrupt 0 input / timer 0 gate control input

P3.3 / INT1:

External interrupt 1 input / timer 1 gate control input

P3.4 / T0:

Timer 0 counter input

P3.5 / T1:

Timer 1 counter input

P3.6 / WR:

External Data Memory write strobe; latches the data byte from port 0 into the external data memory

P3.7 / RD:

External Data Memory read strobe; Enables the external data memory.

In the T89C51AC2 Port 3 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

P4.0:1

I/O

Port 4:

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are

pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are

being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-

up transistor.

In the T89C51AC2 Port 3 can sink or source 5mA. It can drive CMOS inputs without external pull-ups.

RESET

I/O

Reset:

A high level on this pin during two machine cycles while the oscillator is running resets the device. An

internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC.

ALE

ALE:

An Address Latch Enable output for latching the low byte of the address during accesses to the external

memory. The ALE is activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external

data memory access. When instructions are executed from an internal FLASH (EA = 1), ALE generation

can be disabled by the software.

PSEN

PSEN:

The Program Store Enable output is a control signal that enables the external program memory of the bus

during external fetch operations. It is activated twice each machine cycle during fetches from the external

program memory. (However, when executing outside of the external program memory two activations of

PSEN are skipped during each access to the external Data memory). The PSEN is not activated during

fetches from the internal data memory.

EA:

When External Access is held at the high level, instructions are fetched from the internal FLASH when

the program counter is less then 8000H. When held at the low level, CANARY fetches all instructions

from the external program memory

XTAL1

XTAL1:

Input of the inverting oscillator amplifier and input of the internal clock generator circuits.

To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left

unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained.

XTAL2

XTAL2:

Output from the inverting oscillator amplifier.

Pin Name

Type

Description

T89C51AC2-RLSI-M 数据表(PDF) 5 Page - ATMEL Corporation

T89C51AC2-RLSI-M 数据表(HTML) 5 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载