T89C51AC2-RLSI-M datasheet(51/117 Pages) ATMEL

51 / 117 page

Draft.A - March 30, 2001

Preview - Confidential

T89C51AC2

11. Serial I/O Port

The T89C51AC2 I/O serial port is compatible with the I/O serial port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous

Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and

reception can occur simultaneously and at different baud rates

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

Figure 33. Serial I/O Port Block Diagram

11.1. Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes. To enable the framing bit error detection

feature, set SMOD0 bit in PCON register.

Figure 34. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop

bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit

is not found, the Framing Error bit (FE) in SCON register bit is set.

Write SBUF

SBUF

Transmitter

SBUF

Receiver

IB Bus

Mode 0 Transmit

Receive

Shift register

Load SBUF

Read SBUF

SCON

Interrupt Request

Serial Port

TXD

RXD

RB8

TB8

REN

SM2

SM1

SM0/FE

IDL

GF0

GF1

POF

SMOD0

SMOD1

To UART framing error control

SM0 to UART mode control

Set FE bit if stop bit is 0 (framing error)

T89C51AC2-RLSI-M 数据表(PDF) 51 Page - ATMEL Corporation

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