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T89C51AC2-RLSI-M 数据表(PDF) 17 Page - ATMEL Corporation |
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T89C51AC2-RLSI-M 数据表(HTML) 17 Page - ATMEL Corporation |
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17 / 117 page  Draft.A - March 30, 2001 17 Preview - Confidential T89C51AC2 6.3. Register CKCON (S:8Fh) Clock Control Register NOTE: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect. Reset Value = 0000 0000b Figure 7. CKCON Register 7 6 5 4 3 2 1 0 - WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6 WDX2 Watchdog clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 5 PCAX2 Programmable Counter Array clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 4 SIX2 Enhanced UART clock (MODE 0 and 2) (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 3 T2X2 Timer2 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 2 T1X2 Timer1 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 1 T0X2 Timer0 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 0X2 CPU clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits. |
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