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T89C51AC2-RLSI-M 数据表(PDF) 58 Page - ATMEL Corporation |
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T89C51AC2-RLSI-M 数据表(HTML) 58 Page - ATMEL Corporation |
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58 / 117 page ![]() 58 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 Figure 42. Timer/Counter x (x= 0 or 1) in Mode 0 12.3.2. Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 43). The selected input increments TL0 register. Figure 43. Timer/Counter x (x= 0 or 1) in Mode 1 12.3.3. Mode 2 (8-bit Timer with Auto-Reload) Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads from TH0 register (see Figure 44). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any time by writing it to TH0 register. Figure 44. Timer/Counter x (x= 0 or 1) in Mode 2 PERIPH CLOCK TRx TCON reg TFx TCON reg 0 1 GATEx TMOD reg ÷ 6 Overflow Timer x Interrupt Request C/Tx# TMOD reg TLx (5 bits) THx (8 bits) INTx# Tx TRx TCON reg TFx TCON reg 0 1 GATEx TMOD reg Overflow Timer x Interrupt Request C/Tx# TMOD reg TLx (8 bits) THx (8 bits) INTx# Tx PERIPH CLOCK ÷ 6 TRx TCON reg TFx TCON reg 0 1 GATEx TMOD reg Overflow Timer x Interrupt Request C/Tx# TMOD reg TLx (8 bits) THx (8 bits) INTx# Tx PERIPH CLOCK ÷ 6 |
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