| 数据搜索系统,热门电子元器件搜索 |
|
HD64F2149YV 数据表(PDF) 356 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD64F2149YV 数据表(HTML) 356 Page - Renesas Technology Corp |
|
356 / 1075 page ![]() Section 11 16-Bit Free-Running Timer Rev. 3.00 Jan 18, 2006 page 328 of 1044 REJ09B0280-0300 External Clock: If external clock input is selected by bits CKS1 and CKS0 in TCR, FRC increments on the rising edge of the external clock signal. The pulse width of the external clock signal must be at least 1.5 system clock ( φ) periods. The counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods. Figure 11.4 shows the increment timing. N + 1 N FRC input clock φ FRC External clock input pin Figure 11.4 Increment Timing with External Clock Source |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |