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HD64F2149YV 数据表(PDF) 359 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 359 Page - Renesas Technology Corp |
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359 / 1075 page  Section 11 16-Bit Free-Running Timer Rev. 3.00 Jan 18, 2006 page 331 of 1044 REJ09B0280-0300 Input capture signal φ Input capture input pin T1 T2 ICRA/B/C/D read cycle Figure 11.8 Input Capture Signal Timing (Input Capture Input when ICRA/B/C/D is Read) Buffered Input Capture Input Timing: ICRC and ICRD can operate as buffers for ICRA and ICRB. Figure 11.9 shows how input capture operates when ICRA and ICRC are used in buffer mode and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDG A = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA. n n + 1 N N + 1 M n n N mM M n φ FTIA Input capture signal FRC ICRA ICRC Figure 11.9 Buffered Input Capture Timing (Usual Case) |
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