HD64F2149YV datasheet(390/1075 Pages) RENESAS

390 / 1075 page

Section 12 8-Bit Timers

Rev. 3.00 Jan 18, 2006 page 362 of 1044

REJ09B0280-0300

12.2.7

System Control Register (SYSCR)

CS2E

R/W

IOSE

R/W

INTM1

INTM0

R/W

XRST

RAME

R/W

NMIEG

R/W

HIE

R/W

Bit

Initial value

Read/Write

Only bit 1 is described here. For details on functions not related to the 8-bit timers, see sections

3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules.

Bit 1—Host Interface Enable (HIE): Controls CPU access to 8-bit timer (channel X and Y) data

registers and control registers, and timer connection control registers.

Bit 1

HIE

Description

CPU access to 8-bit timer (channel X and Y) data registers and control

registers, and timer connection control registers, is enabled

(Initial value)

CPU access to 8-bit timer (channel X and Y) data registers and control registers, and

timer connection control registers, is disabled

12.2.8

Timer Connection Register S (TCONRS)

TMRX/Y

R/W

ISGENE

R/W

HOMOD1

R/W

HOMOD0

R/W

VOMOD1

R/W

CLMOD0

R/W

VOMOD0

R/W

CLMOD1

R/W

Bit

Initial value

Read/Write

TCONRS is an 8-bit readable/writable register that controls access to the TMRX and TMRY

registers and timer connection operation.

TCONRS is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—TMRX/TMRY Access Select (TMRX/Y): The TMRX and TMRY registers can only be

accessed when the HIE bit in SYSCR is cleared to 0. Some of the TMRX registers and the TMRY

registers are assigned to the same memory space addresses (H'FFF0 to H'FFF5), and the TMRX/Y

bit determines which registers are accessed.

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