HD64F2149YV datasheet(392/1075 Pages) RENESAS

392 / 1075 page

Section 12 8-Bit Timers

Rev. 3.00 Jan 18, 2006 page 364 of 1044

REJ09B0280-0300

12.2.11

Input Capture Registers R and F (TICRR, TICRF) [TMRX Additional Functions]

Bit

Initial value

Read/Write

TICRR and TICRF are 8-bit read-only registers. When the ICST bit in TCONRI is set to 1,

TICRR and TICRF capture the contents of TCNT successively on the rise and fall of the external

reset input. When one capture operation ends, the ICST bit is cleared to 0.

TICRR and TICRF are each initialized to H'00 by a reset and in hardware standby mode.

The TICRR and TICRF functions are used in timer connection. For details, see section 12.3.6,

Input Capture Operation and section 13, Timer Connection.

12.2.12

Timer Input Select Register (TISR) [TMRY Additional Function]

—

R/W

—

Bit

Initial value

Read/Write

TISR is an 8-bit readable/writable register that selects the external clock/reset signal source for the

counter.

TISR is initialized to H'FE by a reset and in hardware standby mode.

Bits 7 to 1—Reserved: Do not write 0 to these bits.

Bit 0—Input Select (IS): Selects the internal synchronization signal (IVG signal) or the timer

clock/reset input pin (VSYNCI/TMIY (TMCIY/TMRIY)) as the external clock/reset signal source

for the counter.

Bit 0

Description

IVG signal is selected

(Initial value)

VSYNCI/TMIY (TMCIY/TMRIY) is selected

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