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HD64F2149YV 数据表(PDF) 396 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 396 Page - Renesas Technology Corp |
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396 / 1075 page  Section 12 8-Bit Timers Rev. 3.00 Jan 18, 2006 page 368 of 1044 REJ09B0280-0300 Timer Output Timing: When compare-match A or B occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in TCSR. Depending on these bits, the output can remain the same, be set to 0, be set to 1, or toggle. Figure 12.5 shows the timing when the output is set to toggle at compare-match A. φ Compare-match A signal Timer output pin Figure 12.5 Timing of Timer Output Timing of Compare-Match Clear: TCNT is cleared when compare-match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 12.6 shows the timing of this operation. φ N H'00 Compare-match signal TCNT Figure 12.6 Timing of Compare-Match Clear |
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