HD64F2149YV datasheet(462/1075 Pages) RENESAS

462 / 1075 page

Section 15 Serial Communication Interface (SCI, IrDA)

Rev. 3.00 Jan 18, 2006 page 434 of 1044

REJ09B0280-0300

Bit 3

STOP

Description

01 stop bit*

(Initial value)

2 stop bits*

Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character

before it is sent.

2. In transmission, two 1 bits (stop bits) are added to the end of a transmit character

before it is sent.

In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second

stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit

character.

Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format

is selected, the PE bit and O/

E bit parity settings are invalid. The MP bit setting is only valid in

asynchronous mode; it is invalid in synchronous mode.

For details of the multiprocessor communication function, see section 15.3.3, Multiprocessor

Communication Function.

Bit 2

Description

Multiprocessor function disabled

(Initial value)

Multiprocessor format selected

Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the

baud rate generator. The clock source can be selected from

φ, φ/4, φ/16, and φ/64, according to the

setting of bits CKS1 and CKS0.

For the relation between the clock source, the bit rate register setting, and the baud rate, see

section 15.2.8, Bit Rate Register (BRR).

Bit 1

Bit 0

CKS1

CKS0

Description

φ clock

(Initial value)

φ/4 clock

φ/16 clock

φ/64 clock

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