HD64F2149YV datasheet(532/1075 Pages) RENESAS

部件名	HD64F2149YV

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

532 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 504 of 1044

REJ09B0280-0300

Bit 7

MLS

Description

MSB-first

(Initial value)

LSB-first

Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data

and the acknowledge bit, in master mode with the I

2C bus format. When WAIT is set to 1, after the

fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins

(with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the

acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred

consecutively with no wait inserted.

The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the

WAIT setting.

The setting of this bit is invalid in slave mode.

Bit 6

WAIT

Description

Data and acknowledge bits transferred consecutively

(Initial value)

Wait inserted between data and acknowledge bits

HD64F2149YV 数据表(PDF) 532 Page - Renesas Technology Corp